library verilog;
use verilog.vl_types.all;
entity clock_generator is
    port(
        clock8          : out    vl_logic;
        reset           : in     vl_logic;
        clock_in        : in     vl_logic;
        clock50         : out    vl_logic;
        clk16           : out    vl_logic;
        clock_PS1       : out    vl_logic;
        clock_PS2       : out    vl_logic;
        clock_PS3       : out    vl_logic
    );
end clock_generator;
